Name
Abstract | ||
|---|---|---|
This paper proposes a coarse-grained dynamically reconfigurable architecture that offers flexible reliability to deal with soft errors and aging. The notion of a cluster is introduced as a basic architectural element; each cluster can select four operation modes with different levels of spatial redundancy and area efficiency. We evaluate the aging effect due to negative bias temperature instability and illustrate that periodically alternating active cells with resting ones will greatly mitigate the effects of the aging process with a negligible power overhead. The area of circuits that are added for immunity to soft errors and for mitigating aging effects is 29.3% of the proposed reconfigurable device. A fault-tolerance evaluation of a Viterbi decoder mapped on the architecture suggests that there is a considerable tradeoff between reliability and area overhead. Finally, we design and fabricate a test chip that contains a 4$\,\times\,$8 cluster array in a 65-nm process and demonstrate its immunity to soft errors. Accelerated tests using an alpha particle foil showed that the mean time to failure and failure in time are well characterized with the number of sensitive bits and that our architecture can trade off soft error immunity with the area of implementation. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/TVLSI.2012.2228015 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | Field | DocType |
Viterbi decoding,ageing,fault tolerance,integrated circuit design,integrated circuit reliability,integrated circuit testing,life testing,negative bias temperature instability,radiation hardening (electronics),Viterbi decoder,accelerated tests,aging effects,alpha particle foil,area efficiency,coarse-grained dynamically reconfigurable architecture,fault tolerance evaluation,flexible reliability,negative bias temperature instability,periodically alternating active cells,power overhead,size 65 nm,soft error immunity,spatial redundancy,test chip,Aging,coarse-grained architecture,reconfigurability,reliability,soft error | Mean time between failures,Soft error,Computer science,Chip,Real-time computing,Electronic engineering,Integrated circuit design,Redundancy (engineering),Fault tolerance,Negative-bias temperature instability,Viterbi decoder,Embedded system | Journal |
Volume | Issue | ISSN |
21 | 12 | 1063-8210 |
Citations | PageRank | References |
5 | 0.43 | 0 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Dawood Alnajiar | 1 | 34 | 3.63 |
| Hiroaki Konoura | 2 | 36 | 5.00 |
| Younghun Ko | 3 | 30 | 2.12 |
| Yukio Mitsuyama | 4 | 134 | 20.01 |
| Masanori Hashimoto | 5 | 462 | 79.39 |
| Takao Onoye | 6 | 329 | 68.21 |