Paper Info
Title
ARCS: an architectural level communication driven simulator
Abstract
Simulators for digital systems operate at a variety of levels of abstraction varying from detailed analog and switch level modeling of the transistor to cycle based descriptions of entire systems. We propose an even higher level simulator, called ARCS, based on the abstraction of an asynchronous communication event rather than of a clock cycle. Modeling systems at this level allows architectural level exploration of the design space before cycle-level details are available, and also allows the same framework to be used to refine architectural level simulations into more detailed simulations with increasingly fine grained notions of timing. The ARCS simulation framework uses concurrently operating threads in Java with communicating sequential processes (CSP) semantics as a natural expression of communication between concurrent hardware. To avoid synchronization bottlenecks ARCS models time using a communication driven clockwork model which allows for both user configurable runtime viewing of the simulation and post processing of complete simulation timing data.
Year
DOI
Venue
2004
10.1145/988952.988970
ACM Great Lakes Symposium on VLSI
Keywords
Field
DocType
asynchronous communication event,detailed simulation,arcs models time,architectural level exploration,architectural level communication,complete simulation timing data,arcs simulation framework,architectural level simulation,clock cycle,switch level modeling,higher level simulator,java,asynchronous communication
Computer science,Real-time computing,Distributed computing,Asynchronous communication,Synchronization,Computer architecture,Simulation,Communicating sequential processes,Thread (computing),Logic simulation,Cycles per instruction,Java,Semantics
Conference
ISBN
Citations 
PageRank 
1-58113-853-9
0
0.34
References 
Authors
11
3
Name
Order
Citations
PageRank
Dave Nellans100.34
Vamshi Krishna Kadaru200.34
Erik Brunvand350966.09