Name
Title | ||
|---|---|---|
A 0.15-Mu M Fd-Soi Substrate Bias Control Sram With Inter-Die Variability Compensation Scheme |
Abstract | ||
|---|---|---|
We propose a novel substrate-bias control scheme for an FD-SOI SRAM that suppresses inter-die variability. The proposed circuits detect inter-die threshold-voltage variation automatically, and then maximize read/write margins of memory cells to supply the substrate bias. We confirmed that a 486-kb 61 SRAM operates at 0.42 V, in which an FS corner can be compared as much as 0.14 V or more. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1587/transele.E95.C.579 | IEICE TRANSACTIONS ON ELECTRONICS |
Keywords | Field | DocType |
SRAM, FD-SOI, Inter-die variation | Soi substrate,Static random-access memory,Electronic engineering,Engineering,Electronic circuit,Electrical engineering | Journal |
Volume | Issue | ISSN |
E95C | 4 | 1745-1353 |
Citations | PageRank | References |
0 | 0.34 | 2 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shunsuke Okumura | 1 | 63 | 12.54 |
| Hidehiro Fujiwara | 2 | 72 | 12.67 |
| Kosuke Yamaguchi | 3 | 0 | 1.01 |
| Shusuke Yoshimoto | 4 | 30 | 12.56 |
| Masahiko Yoshimoto | 5 | 0 | 0.34 |
| Hiroshi Kawaguchi | 6 | 37 | 21.08 |