Name
Abstract | ||
|---|---|---|
Datapaths for media signal processing are typically built using programmable computational elements such as adders and multipliers, which can be run-time reconfigured to operate on simple integers with 8, 16, or 32 bits of precision. In this brief, a new high-speed energy-efficient reconfigurable adder for media signal processing is presented. The proposed circuit is based on carry-propagation schemes and can be partitioned to perform one 64-, two 32-, four 16-, and eight 8-bit additions. When the Austria Mikro System (AMS) 0.35 µm 2-poly 3-metal 3.3 V CMOS (CSD) process is used to produce layout, a worst propagation delay of about 4.9 ns and an average energy dissipation of about 181 µW/MHz are obtained. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1109/TVLSI.2003.817109 | IEEE Trans. VLSI Syst. |
Keywords | Field | DocType |
CMOS logic circuits,adders,high-speed integrated circuits,low-power electronics,reconfigurable architectures,0.35 micron,3.3 V,64 bit,CMOS circuit,carry propagation,datapath,energy dissipation,energy efficiency,high-speed reconfigurable binary adder,multimedia signal processing,programmable computational element,propagation delay | Integrated circuit layout,Signal processing,Datapath,Propagation delay,Adder,Computer science,Electronic engineering,CMOS,Carry-save adder,Reconfigurable computing | Journal |
Volume | Issue | ISSN |
11 | 5 | 1063-8210 |
Citations | PageRank | References |
4 | 0.52 | 10 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Stefania Perri | 1 | 264 | 33.11 |
| Pasquale Corsonello | 2 | 278 | 38.06 |
| Giuseppe Cocorullo | 3 | 106 | 17.00 |