Giuseppe Cocorullo

Author Info

Name	Affiliation	Papers
GIUSEPPE COCORULLO	Department of Electronics Computer Science and Systems, University of Calabria, Rende, Italy	35
Collaborators	Citations	PageRank
22	106	17.00
Referers	Referees	References
271	579	227

Search Limit

100579

Publications (35 rows)

Collaborators (22 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Robust and High-Performance Machine Vision System for Automatic Quality Inspection in Assembly Processes	0	0.34	2022
Multimodal background subtraction for high-performance embedded systems	0	0.34	2019
A Smart Torque Control for a High Efficiency 4WD Electric Vehicle.	0	0.34	2018
Design of Efficient BCD Adders in Quantum-Dot Cellular Automata.	2	0.41	2017
An efficient hardware-oriented stereo matching algorithm.	2	0.35	2016
Design Of Efficient Qca Multiplexers	0	0.34	2016
A novel background subtraction method based on color invariants and grayscale levels	0	0.34	2014
Adaptive Census Transform: A novel hardware-oriented stereovision algorithm	8	0.61	2013
Low-cost FPGA stereo vision system for real time disparity maps calculation	9	0.48	2012
Corrections to "settling time optimization for three-stage CMOS amplifier topologies"	0	0.34	2010
Analysis of op-amp phase margin impact on SC SigmaDelta modulator performance	0	0.34	2010
Analysis of the Impact of High-Order Integrator Dynamics on SC Sigma-Delta Modulator Performances	3	0.55	2010
Corrections to “Settling Time Optimization for Three-Stage CMOS Amplifier Topologies” [Dec 09 2569-2582]	0	0.34	2010
Effect of OP-amp Phase Margin on SC SigmaDelta Modulator Performances.	0	0.34	2009
A New Dynamic Logic Circuit Design for an Effective Trade-Off between Noise-Immunity, Performance and Energy Dissipation	0	0.34	2008
A matrix product accelerator for field programmable systems on chip	10	0.93	2008
Design Procedure for Settling Time Minimization in Three-Stage Nested-Miller Amplifiers	16	0.87	2008
Settling-Optimization-Based Design Approach for Three-Stage Nested-Miller Amplifiers	0	0.34	2008
Design and Implementation of a 90nm Low bit-rate Image Compression Core	0	0.34	2007
Techniques for leakage energy reduction in deep submicrometer cache memories	12	0.95	2006
Leakage energy reduction techniques in deep submicron cache memories: a comparative study	0	0.34	2006
A simple MOSFET parasitic capacitance model and its application to repeater insertion technique	0	0.34	2006
Output resistance scaling model for deep-submicron cmos buffers for timing performance optimisation	0	0.34	2005
A high-performance fully reconfigurable FPGA-based 2D convolution processor	17	1.24	2005
Microprocessor-based FPGA implementation of SPIHT image compression subsystems	4	0.41	2005
Fast low-power 64-bit modular hybrid adder	0	0.34	2005
Variable precision arithmetic circuits for FPGA-based multimedia processors	8	0.74	2004
Variable Precision Multipliers for FPGA-Based Reconfigurable Computing Systems	3	0.70	2003
A high-speed energy-efficient 64-bit reconfigurable binary adder	4	0.52	2003
Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines	2	0.77	2002
VLSI circuits for low-power high-speed asynchronous addition	0	0.34	2002
VLSI Implementation of a Low-Power High-Speed Self-Timed Adder	1	0.37	2000
Area-time-power tradeoff in cellular arrays VLSI implementations	3	0.64	2000
A time-domain model for power dissipation of CMOS buffers driving lossy transmission lines	0	0.34	1999
High performance VLSI modules for division and square root	2	0.37	1998