Name
Abstract | ||
|---|---|---|
SoC (System on a Chip), which can be utilized for various applications, can be implemented with FPGA. Therefore, many products and research testbeds which implement a processor in FPGA are emerging, and many softcore processors are getting released. Multithread architecture will be possibly adopted as a softcore processor. In this paper, we implement an SMT processor with FPGA and evaluate its Performance, amount of hardware costs and its clock frequency. Moreover, from the characteristic of FPGA, since we can reconfigure cache statically, we propose a new model which reconfigures the configuration of cache according with a being executed program. As a result of implementing an SMT processor, though we have confirmed improvement of performance by SMT implementation with increased hardware of about 1.3 times compared with a conventional superscalar processor. SMT processor runs with clock frequency of about 80MHz. As a result of cache evaluation, we have found the optimal cache configurations for programs with our designed cache. And we have confirmed performance improvement with statically reconfigurable cache. |
Year | Venue | Keywords |
|---|---|---|
2005 | PDPTA '05: PROCEEDINGS OF THE 2005 INTERNATIONAL CONFERENCE ON PARALLEL AND DISTRIBUTED PROCESSING TECHNIQUES AND APPLICATIONS, VOLS 1-3 | FPGA, SMT, reconfigurable cache |
Field | DocType | Citations |
Computer architecture,Computer science,Cache,Parallel computing,Field-programmable gate array,FPGA prototype,Reconfigurable computing | Conference | 2 |
PageRank | References | Authors |
0.46 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshiyasu Ogasawara | 1 | 18 | 4.05 |
| Norito Kato | 2 | 3 | 1.19 |
| Masanori Yamato | 3 | 3 | 1.19 |
| Mikiko Sato | 4 | 22 | 11.53 |
| Koichi Sasada | 5 | 9 | 2.50 |
| Kaname Uchikura | 6 | 5 | 1.95 |
| Mitaro Namiki | 7 | 97 | 20.69 |
| Hironori Nakajo | 8 | 69 | 20.66 |