Koichi Sasada - Citegraph

Author Info

Name	Affiliation	Papers
KOICHI SASADA	Tokyo Univ Agr & Technol, Koganei, Tokyo, Japan	6
Collaborators	Citations	PageRank
11	9	2.50
Referers	Referees	References
27	41	13

Publications (6 rows)

Collaborators (11 rows)

Referers (27 rows)

Referees (41 rows)

Title	Citations	PageRank	Year
Towards Reconfigurable Cache Memory for a Multithreaded Processor	2	0.42	2006
A Model of Implementable SMT Processor on FPGA	0	0.34	2006
A New Model Of Reconfigurable Cache For An Smt Processor And Its Fpga Implementation	2	0.46	2005
YARV: yet another RubyVM: innovating the ruby interpreter	4	0.56	2005
Development Of A Thread Scheduler For Smt Processor Architecture	1	0.40	2005
Dynamic Allocation Of Physical Register Banks For An Smt Processor	0	0.34	2004

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