Name
Abstract | ||
|---|---|---|
Redundant binary number appears to be appropriate for high-speed arithmetic operation, but the delay and hardware cost associated with the conversion from redundant binary (RB) to natural binary (NB) number is still a challenging task. In the present investigation a simple approach has been adopted to achieve high speed with lesser hardware and power saving. A circuit level approach has been adopted to implement the equivalent bit conversion algorithm (EBCA) (Kim et al. IEEE Journal of Solid State Circuits 36:1538-1544, 2001, 38:159-160, 2003) for RB to NB conversion. The circuit is designed based on exploration of predictable carry out feature of EBCA algorithm. This implementation concludes a significant delay power product and component complexity advantage for a 64-bit RB to NB conversion using novel carry-look-ahead equivalent bit converter. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/s11265-009-0392-x | Signal Processing Systems |
Keywords | Field | DocType |
Redundant binary number,Equivalent bit conversion algorithm,Redundant binary to natural binary converter,Carry-look-ahead adder | Bit-length,Power saving,Computer science,Real-time computing,Binary number,IEEE Journal of Solid-State Circuits | Journal |
Volume | Issue | ISSN |
59 | 3 | 1939-8018 |
Citations | PageRank | References |
3 | 0.45 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. K. Sahoo | 1 | 3 | 0.45 |
| Anu Gupta | 2 | 8 | 3.99 |
| Abhijit R. Asati | 3 | 13 | 5.70 |
| Chandra Shekhar | 4 | 19 | 9.71 |