Chandra Shekhar - Citegraph

Author Info

Name	Affiliation	Papers
CHANDRA SHEKHAR	Central Electronics Engineering Research Institute, Pilani, India	27
Collaborators	Citations	PageRank
45	19	9.71
Referers	Referees	References
69	310	129

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100310

Publications (27 rows)

Collaborators (45 rows)

Referers (69 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Real time FPGA implementation of a high speed and area optimized Harris corner detection algorithm	0	0.34	2021
Power- And Area-Optimized High-Level Synthesis Implementation Of A Digital Down Converter For Software-Defined Radio Applications	1	0.37	2021
High-Speed And Area-Efficient Sobel Edge Detector On Field-Programmable Gate Array For Artificial Intelligence And Machine Learning Applications	1	0.35	2021
Optimal control of a service system with emergency vacation using bat algorithm.	0	0.34	2020
Warm-spare provisioning Computing Network with Switching Failure, Common Cause Failure, Vacation Interruption, and Synchronized Reneging	0	0.34	2020
Load sharing redundant repairable systems with switching and reboot delay	0	0.34	2020
High-Level synthesis assisted design and verification framework for automotive radar processors	0	0.34	2020
Modified Bessel Series Solution Of The Single Server Queueing Model With Feedback	0	0.34	2019
A New XOR-FREE Approach to Implement Walsh Sequences	0	0.34	2019
Reliability prediction of fault tolerant machining system with reboot and recovery delay.	0	0.34	2018
Memory Efficient VLSI Implementation of Real-Time Motion Detection System Using FPGA Platform.	0	0.34	2017
Real-Time FPGA-Based Object Tracker with Automatic Pan-Tilt Features for Smart Video Surveillance Systems.	2	0.37	2017
N-policy for a repairable redundant machining system with controlled rates.	0	0.34	2016
An FPGA-Based Architecture for Local Similarity Measure for Image/Video Processing Applications	1	0.35	2015
Double orbit finite retrial queues with priority customers and service interruptions	2	0.39	2015
A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding Algorithm	1	0.38	2014
Queueing analysis of two unreliable servers machining system with switching and common cause failure	1	0.36	2013
Synthesis of Analog IC Building Blocks	0	0.34	2011
A Novel Redundant Binary Number to Natural Binary Number Converter	3	0.45	2010
Moving Object Tracking Using Object Segmentation	2	0.39	2010
Dual channel addition based FFT processor architecture for signal and image processing	0	0.34	2009
Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital CMOS Inverter Design for a Given Fanout Load	0	0.34	2009
Figure-of-merit-based area-constrained design of differential amplifiers	1	0.38	2008
Processor-shared service systems with queue-dependent processors	2	0.38	2005
Evaluation of device parameters of HfO2/SiO2/Si gate dielectric stack for MOSFETs	0	0.34	2005
Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis	2	0.47	2004
High frequency behaviour of electron transport in silicon and its implication for drain conductance of MOS transistors	0	0.34	2001