Name
Title | ||
|---|---|---|
Alleviating the Data Memory Bandwidth Bottleneck in Coarse-Grained Reconfigurable Arrays |
Abstract | ||
|---|---|---|
It is widely known that parallel operation execution in multiprocessor systems generates a respective increase in memory accesses. Since the memory and bus subsystems provide a limited access bandwidth, the applications performance cannot be that high as the multiprocessor system capabilities promise. This is the case for the 2-Dimensional coarse-grained reconfigurable arrays for which a mapping methodology that aims in improving the mapped applications驴 performance by alleviating the data bandwidth bottleneck, is presented in this paper. This is achieved by exploiting the applications驴 data reuse opportunities both at the data dependence and source code level and the architecture驴s foreground memory. The methodology considers a realistic 2-Dimensional coarsegrained reconfigurable architecture template, which can model the majority of the existing coarse-grained reconfigurable array architectures. The experimental results show a significant reduction in both execution time and memory accesses for two architecture scenarios that has been achieved by the application of the proposed methodology on a representative set of DSP applications. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/ASAP.2005.12 | ASAP |
Keywords | Field | DocType |
foreground memory,data reuse opportunity,bandwidth bottleneck,applications performance,data memory,architecture scenario,data bandwidth bottleneck,existing coarse-grained reconfigurable array,memory access,2-dimensional coarse-grained reconfigurable array,coarse-grained reconfigurable arrays,data dependence,2-dimensional coarsegrained reconfigurable architecture,parallel processing,source code,field programmable gate arrays,embedded system,memory bandwidth,bandwidth,digital signal processing,2 dimensional,network topology | Bottleneck,Digital signal processing,Computer architecture,Uniform memory access,Computer science,Source code,Parallel computing,Field-programmable gate array,Network topology,Multiprocessing,Bandwidth (signal processing),Embedded system | Conference |
ISSN | ISBN | Citations |
2160-0511 | 0-7695-2407-9 | 11 |
PageRank | References | Authors |
0.76 | 8 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gregory Dimitroulakos | 1 | 47 | 7.14 |
| Michalis D. Galanis | 2 | 94 | 15.60 |
| Costas E Goutis | 3 | 186 | 25.76 |