Paper Info
Title
Performance gains from partitioning embedded applications in Processor-FPGA socs
Abstract
In this paper, we propose a hardware/software partitioning method for improving performance in single-chip embedded systems comprised by processor and Field Programmable Gate Array reconfigurable logic. Speedups are achieved by executing critical software parts on the reconfigurable logic. A generic hybrid System-on-Chip platform, which can model existing processor-FPGA systems, is considered. The partitioning flow utilizes an automated analysis procedure at the basic-block level for detecting kernels in software. Three different instances of the considered generic platform and two sets of benchmarks are used in the experiments. For the systems composed by 32-bit processors the speedup of five applications ranges from 1.3 to 3.7 relative to an all software solution. For an 8-bit platform, the speedups of eight DSP algorithms are considerably greater, since they range from 3.2 to 68.4.
Year
DOI
Venue
2005
10.1007/11556930_26
PATMOS
Keywords
Field
DocType
reconfigurable logic,generic hybrid system-on-chip platform,32-bit processor,generic platform,field programmable gate array,partitioning flow,8-bit platform,processor-fpga socs,critical software part,performance gain,embedded application,software solution,dsp algorithm,chip,hybrid system,embedded system
32-bit,System on a chip,Computer science,Digital signal processor,Parallel computing,Field-programmable gate array,Real-time computing,Reduced instruction set computing,Software,Hybrid system,Speedup,Embedded system
Conference
Volume
ISSN
ISBN
3728
0302-9743
3-540-29013-3
Citations 
PageRank 
References 
0
0.34
9
Authors
3
Name
Order
Citations
PageRank
Michalis D. Galanis19415.60
Gregory Dimitroulakos2477.14
Costas E Goutis318625.76