Name
Abstract | ||
|---|---|---|
This paper presents an SRAM architecture employing a multiword-based ECC (MECC) scheme for soft error mitigation and a row virtual ground technique for array leakage reduction. The MECC combines four data words to form a 128 bit composite ECC word, two of which are interleaved in a row to mitigate cosmic neutron-induced multi-bit errors. The use of a composite word reduces the number of check-bits... |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1109/JSSC.2009.2021088 | IEEE Journal of Solid-State Circuits |
Keywords | Field | DocType |
Random access memory,Error correction codes,Semiconductor device modeling,CMOS technology,Writing,Energy consumption,Error analysis,Delay,Life estimation,Neutrons | Virtual ground,Logic gate,Soft error,Computer science,Error detection and correction,CMOS,Electronic engineering,Static random-access memory,Word (computer architecture),128-bit | Journal |
Volume | Issue | ISSN |
44 | 9 | 0018-9200 |
Citations | PageRank | References |
8 | 0.67 | 7 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shah M. Jahinuzzaman | 1 | 49 | 6.08 |
| Jaspal Singh Shah | 2 | 21 | 2.12 |
| David J. Rennie | 3 | 8 | 1.00 |
| Manoj Sachdev | 4 | 669 | 88.45 |