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SHAH M. JAHINUZZAMAN
Author Info
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Name
Affiliation
Papers
SHAH M. JAHINUZZAMAN
Univ Waterloo, Waterloo, ON, Canada
9
Collaborators
Citations
PageRank
11
49
6.08
Referers
Referees
References
147
76
46
Search Limit
100
147
Publications (9 rows)
Collaborators (11 rows)
Referers (100 rows)
Referees (76 rows)
Title
Citations
PageRank
Year
Susceptibility of planar and 3D tri-gate technologies to muon-induced single event upsets
0
0.34
2015
A read-decoupled gated-ground SRAM architecture for low-power embedded memories
0
0.34
2012
A 7T SRAM bit-cell for low-power embedded memories
0
0.34
2011
A scalable offset-cancelled current/voltage sense amplifier
1
0.42
2010
An analytical model for soft error critical charge of nanometric SRAMs
22
1.78
2009
Design and Analysis of A 5.3-pJ 64-kb Gated Ground SRAM With Multiword ECC
8
0.67
2009
A Multiword Based High Speed ECC Scheme for Low- voltage Embedded SRAMs
4
0.45
2008
Investigation of Process Impact on Soft Error Susceptibility of Nanometric SRAMs Using a Compact Critical Charge Model
9
0.75
2008
Dynamic Data Stability in Low-power SRAM Design.
5
1.00
2007
1