Abstract | ||
---|---|---|
High quality Built-In Self Test (BIST) needs to efficiently tackle the coverage of random-pattern-resistant (r.p.r) defects. Several techniques have been proposed to cover r.p.r faults at logic level, namely, weighted pseudo-random and mixed-mode. In mixed-mode test pattern generation (TPG) techniques, deterministic tests are added to pseudo-random vectors to detect r.p.r faults. Recently, a RTL mixed-mode TPG technique has been proposed to cover r.p.r defects, the mask-based BIST technique. The purpose of this paper is to present mask-based BIST TPG improvements, namely in two areas: RTL estimation of the test length to be used for each mask, in order to reach high Defects Coverage (DC), and the identification of an optimum mask for each set of nested RTL conditions. Results are used to predict the number of customized vectors for each mask of one ITC'99 benchmark module. |
Year | DOI | Venue |
---|---|---|
2003 | 10.1109/DATE.2003.1253734 | DATE |
Keywords | Field | DocType |
high quality loosely deterministic,mixed-mode test pattern generation,test length,mask-based bist technique,deterministic test,high defects coverage,optimum mask,rtl estimation,bist tpg improvement,high quality,nested rtl condition,rtl test pattern generation,probability,atpg,fault detection,vectors,automatic test pattern generation,system on chip,system on a chip,product development | Automatic test pattern generation,Pattern generation,System on a chip,Logic testing,Computer science,Real-time computing,Logic level,Self test,Built-in self-test | Conference |
ISBN | Citations | PageRank |
0-7695-1870-2 | 6 | 0.59 |
References | Authors | |
10 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
M. B. Santos | 1 | 6 | 0.93 |
J. M. Fernandes | 2 | 10 | 1.01 |
I. C. Teixeira | 3 | 163 | 20.29 |
J. P. Teixeira | 4 | 35 | 2.83 |