| Fault-tolerance in FPGA focusing power reduction or performance enhancement | 0 | 0.34 | 2015 |
| Biped locomotion - Improvement and adaptation | 1 | 0.36 | 2014 |
| Process Variations-Aware Statistical Analysis Framework for Aging Sensors Insertion | 2 | 0.38 | 2013 |
| The influence of clock-gating on NBTI-induced delay degradation | 1 | 0.35 | 2012 |
| Performance Failure Prediction Using Built-In Delay Sensors in FPGAs | 3 | 0.41 | 2011 |
| Predictive error detection by on-line aging monitoring | 5 | 0.57 | 2010 |
| Low-sensitivity to process variations aging sensor for automotive safety-critical applications | 8 | 0.59 | 2010 |
| Programmable aging sensor for automotive safety-critical applications | 13 | 0.69 | 2010 |
| Signal Integrity Enhancement in Digital Circuits | 1 | 0.35 | 2008 |
| Improving the Tolerance of Pipeline Based Circuits to Power Supply or Temperature Variations | 4 | 0.51 | 2007 |
| Enhancing the Tolerance to Power-Supply Instability in Digital Circuits | 0 | 0.34 | 2007 |
| On-line Dynamic Delay Insertion to Improve Signal Integrity in Synchronous Circuits | 0 | 0.34 | 2007 |
| Dynamic Fault Detection in Digital Systems Using Dynamic Voltage Scaling and Multi-Temperature Schemes | 2 | 0.37 | 2006 |
| Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip | 5 | 0.43 | 2005 |
| Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test | 4 | 0.43 | 2005 |
| On High-Quality, Low Energy Built-In Self Test Preparation at RT-Level | 0 | 0.34 | 2004 |
| Modeling and Simulation of Time Domain Faults in Digital Systems | 4 | 0.44 | 2004 |
| RTL Test Pattern Generation for High Quality Loosely Deterministic BIST | 6 | 0.59 | 2003 |
| RTL Design Validation, DFT and Test Pattern Generation for High Defects Coverage | 0 | 0.34 | 2002 |
| Self-checking and fault tolerance quality assessment using fault sampling | 2 | 0.57 | 2002 |
| RTL Level Preparation of High-Quality/Low-Energy/Low-Power BIST | 5 | 0.51 | 2002 |
| Design and Test of a Certifiable ASIC for a Safety-Critical Gas Burner Control System | 5 | 0.57 | 2002 |
| Design and Test of Certifiable ASICs for Safety-Critical Gas Burners Control | 1 | 0.36 | 2001 |
| RTL-Based Functional Test Generation for High Defects Coverage in Digital SOCs | 29 | 2.24 | 2001 |
| Defect-Oriented Verilog Fault Simulation of SoC Macros using a Stratified Fault Sampling Technique | 11 | 0.75 | 1999 |
| Metrics and Criteria for Quality Assessment of Testable Hw/Sw Systems Architectures | 9 | 1.56 | 1999 |
| Defect-oriented test quality assessment using fault sampling and simulation | 6 | 0.57 | 1998 |
| HW/SW specification using OOM techniques | 2 | 0.49 | 1996 |
| Integrated Approach for Circuit and Fault Extraction of VLSI Circuits. | 14 | 1.69 | 1996 |
| A methodology for testability enhancement at layout level | 19 | 2.43 | 1991 |
| A strategy for testability enhancement at layout level | 1 | 0.38 | 1990 |
