Paper Info
Title
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices
Abstract
This paper proposes a BIST (Built-In Self Test) method for testing the PEs (Processing Elements) of multi-context based dynamically reconfigurable processor. We use flipflops existing in PEs to constitute the test circuit which has the function of LFSR (Linear Feedback Shift Register) and MISR (Multiple Input Signature Register) as DFT (Design For Testability). This method can reduce test execution time while maintaining the high rate of fault coverage. Evaluation of the proposed method examined on DRP-1, a coarsegrained Dynamically Reconfiguration Processor developed by NEC electronics in 2002 is presented. The number of test configurations and test execution time can be reduced 59.0% and 89.3% respectively compared to a deterministic test with 4.3% area overhead.
Year
DOI
Venue
2006
10.1109/ETS.2006.10
European Test Symposium
Keywords
Field
DocType
dft,bistbuilt-in self test,built-in self test,linear feedback shift register,test configuration,coarse grained dynamically reconfigurable,drp,pe.,coarse grained dynamically reconfig- urable devices,deterministic test,nec electronics,built-in self-test,multiple input signature register,test circuit,processing elements,test execution time,shift registers,national electric code,fault coverage,design for testability
Design for testing,Shift register,Fault coverage,Computer science,Real-time computing,Electronics,Energy consumption,National Electrical Code,Control reconfiguration,Built-in self-test
Conference
ISSN
ISBN
Citations 
1530-1877
0-7695-2566-0
4
PageRank 
References 
Authors
0.63
7
2
Name
Order
Citations
PageRank
Kentaroh Katoh1346.64
Hideo Ito210017.45