Author Info
Name
Affiliation
Papers
KENTAROH KATOH
Tsuruoka Natl Coll Technol, Dept Elect Engn, Tsuruoka, Yamagata 2638522, Japan
16
Collaborators
Citations 
PageRank 
31
34
6.64
Referers 
Referees 
References 
84
261
104
Search Limit
100261
Title
Citations
PageRank
Year
Erratum to: A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator.00.342015
A low area calibration technique of TDC using variable clock generator for accurate on-line delay measurement10.372015
A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator40.462014
Analog/Mixed-Signal Circuit Design In Nano Cmos Era10.392014
An Analysis of Stochastic Self-Calibration of TDC Using Two Ring Oscillators00.342013
Frequency Stabilization Of Multiple Semiconductor Lasers For Nyquist-Wdm Transmission Systems00.342013
Digital Compensation for Timing Mismatches in Interleaved ADCs10.352013
An on-chip delay measurement technique using signature registers for small-delay defect detection60.532012
A Low Area On-chip Delay Measurement System Using Embedded Delay Measurement Circuit80.602010
A Delay Measurement Technique Using Signature Registers40.492009
Design For Delay Fault Testability Of Dual Circuits Using Master And Slave Scan Paths00.342009
Design For Delay Fault Testability Of 2-Rail Logic Circuits00.342009
Two-Stage Stuck-at Fault Test Data Compression Using Scan Flip-Flops with Delay Fault Testability.00.342008
Fault Tolerant SoC Architecture Design for JPEG2000 using Partial Reconfigurability20.402007
Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices40.632006
Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift30.402005