Name
Abstract | ||
|---|---|---|
SRAM cell stability measurement is traditionally based on static criteria of data stability requiring 3 coincident points in butterfly curves. We introduce dynamic criteria of stability for the cell knowing that the cell operates in a dynamic environment. It reveals that the true noise margin of the cell can be made considerably higher than the SNM once the cell access time is sufficiently shorter than the cell time-constant. This behavior enables enhancing SRAM yield as well as reducing cell operating voltage without compromising reliability. A 40Kb SRAM designed using SVGND scheme exploits the dynamic behavior of the cell in order to increase the stability and reduce the static and dynamic power consumption. The SRAM unit realized in 0.13 mu m CMOS consumes 702uW at 100MHz during write operation and offers a 27pA/Cell leakage current. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/CICC.2007.4405722 | CICC |
Keywords | Field | DocType |
CMOS digital integrated circuits,CMOS memory circuits,SRAM chips,leakage currents,low-power electronics,stability,CMOS integrated circuit,SRAM cell stability,SRAM yield,SVGND scheme,dynamic data stability,frequency 100 MHz,leakage current,low-power SRAM design,noise margin,power 702 muW,size 0.13 mum,storage capacity 40 Kbit,write operation | Access time,Leakage (electronics),Computer science,Electronic engineering,CMOS,Static random-access memory,Dynamic data,Dynamic demand,Noise margin,Low-power electronics | Conference |
Citations | PageRank | References |
5 | 1.00 | 4 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohammad Sharifkhani | 1 | 147 | 25.76 |
| Shah M. Jahinuzzaman | 2 | 49 | 6.08 |
| Manoj Sachdev | 3 | 669 | 88.45 |