Name
Abstract | ||
|---|---|---|
This paper presents a new full parallel circuit for square root extraction based on a modified nonrestoring algorithm. These modifications make it possible to avoid auxiliary systems for the identification of exceptions, such as the zero partial remainder. Moreover, a combined division/square root circuit, with zero latency cycles during operation mode changes, is proposed. Both architectures are structured as pipelined cellular arrays in which carry-select adders are used in order to improve performance. Because non-redundant arithmetic is used, no additional conversion circuitry is required. The achievable performances make the proposed architectures suitable for high speed digital signal processors. |
Year | DOI | Venue |
|---|---|---|
1998 | 10.1016/S0141-9331(98)00082-9 | Microprocessors and Microsystems |
Keywords | Field | DocType |
Computer arithmetic,Division,Square root,Architecture | Adder,Computer science,Digital signal processor,Latency (engineering),Parallel computing,Operation mode,Remainder,Series and parallel circuits,Computer hardware,Square root,Very-large-scale integration | Journal |
Volume | Issue | ISSN |
22 | 5 | 0141-9331 |
Citations | PageRank | References |
2 | 0.37 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Gregorio Cappuccino | 1 | 36 | 10.11 |
| Pasquale Corsonello | 2 | 278 | 38.06 |
| Giuseppe Cocorullo | 3 | 106 | 17.00 |