Paper Info
Title
A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM With Dual-Error Detection and PVT-Tolerant Data-Fetch Scheme.
Abstract
A 1.2 V 4 Gb DDR4 SDRAM is presented in a 30 nm CMOS technology. DDR4 SDRAM is developed to raise memory bandwidth with lower power consumption compared with DDR3 SDRAM. Various functions and circuit techniques are newly adopted to reduce power consumption and secure stable transaction. First, dual error detection scheme is proposed to guarantee the reliability of signals. It is composed of cyclic...
Year
DOI
Venue
2013
10.1109/JSSC.2012.2213512
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
SDRAM,Computer architecture,Power demand,Delay,CMOS integrated circuits,Receivers
Journal
48
Issue
ISSN
Citations 
1
0018-9200
5
PageRank 
References 
Authors
0.71
0
28
Name
Order
Citations
PageRank
Kyomin Sohn1295.15
Taesik Na28512.26
Indal Song3183.56
Yong Shim4162.45
Wonil Bae5161.79
Sanghee Kang6172.87
Dong-Su Lee7203.37
Hangyun Jung8141.42
Seok-Hun Hyun9173.15
Hanki Jeoung10151.80
Ki Won Lee11183.16
Junseok Park1221426.80
Jongeun Lee1342933.71
Byunghyun Lee14293.46
Inwoo Jun15141.42
Juseop Park16141.42
Junghwan Park17141.76
Hundai Choi18172.51
S. Kim1927023.89
Haeyoung Chung20141.76
Young Choi21141.76
Dae-Hee Jung22141.76
Byungchul Kim23263.86
Junghwan Choi2427933.08
Seong-jin Jang259927.16
Chi-Wook Kim26112.16
Jung-Bae Lee2717917.70
Joo-Sun Choi2824629.16