Name
Abstract | ||
|---|---|---|
An area-efficient dynamically reconfigurable architecture is proposed, which is dedicated to media processing. To implement it compact but high performance device, which can be used in consumer applications, the reconfigurable architecture distinctively performs 8-bit operations required for media processing whereas fine-grained operations are executed with the cooperation of a host processor. A heterogeneous reconfigurable array is composed of four types of cells, for which configuration data size is reduced by focusing application domain on media processing. Implementation results show that a multi-standard video decoding can be achieved by the proposed reconfigurable architecture with 1.1 x 1.4 mm(2) in a 90 run CMOS technology. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1093/ietfec/e91-a.12.3651 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
reconfigurable, media processing, multi-standard, area-efficiency, dynamic reconfiguration | Reconfigurable array,Computer architecture,Architecture,Theoretical computer science,CMOS,Application domain,Host processor,Decoding methods,Mathematics,Embedded system | Journal |
Volume | Issue | ISSN |
E91A | 12 | 0916-8508 |
Citations | PageRank | References |
4 | 0.95 | 4 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yukio Mitsuyama | 1 | 134 | 20.01 |
| Kazuma Takahashi | 2 | 4 | 0.95 |
| Rintaro Imai | 3 | 4 | 0.95 |
| Masanori Hashimoto | 4 | 462 | 79.39 |
| Takao Onoye | 5 | 329 | 68.21 |
| Isao Shirakawa | 6 | 220 | 65.34 |