Paper Info
Title
A simplified executable model to evaluate latency and throughput of networks-on-chip
Abstract
This paper proposes a technique that mixes simulation and an analytical method to evaluate the characteristics of Networks-on-Chips (NoCs). The advantage of this technique is to reduce the simulation time by reducing the complexity of the NoC model while still obtaining accurate results for latency and throughput. The basis of this technique is: (i) to send the whole payload data at once in the packet header; (ii) to reduce the NoC simulation complexity by omitting the flit by flit payload forwarding; (iii) to use an algorithm for controlling the release of the packet trailer in order to close the connection at the right time. For the evaluation of this technique, an actor-oriented model of a NoC, JOSELITO, was created. Simulation results show that JOSELITO is in average 2.3 times faster in 88% of the executed case studies than the implementation without using the proposed technique. The worst case simulation results for latency and throughput have, respectively, 5.26% and 0.1% error compared to the corresponding Register Transfer Level (RTL) model.
Year
DOI
Venue
2008
10.1145/1404371.1404420
SBCCI
Keywords
Field
DocType
worst case simulation result,noc simulation complexity,noc model,simulation time,proposed technique,executed case study,actor-oriented model,simulation result,packet header,executable model,flit payload forwarding,network on chip,register transfer level,modeling,integrated circuit,model category
Computer science,Latency (engineering),Network packet,Real-time computing,Electronic engineering,Header,Register-transfer level,Throughput,Trailer,Executable,Payload,Embedded system
Conference
Citations 
PageRank 
References 
9
0.58
17
Authors
7
Name
Order
Citations
PageRank
Luciano Ost144136.69
Fernando Moraes272043.62
Leandro Möller335622.34
Leandro Soares Indrusiak448692.68
Manfred Glesner51121255.04
Sanna Määttä6272.90
Jari Nurmi755683.87