Name
Title | ||
|---|---|---|
A 10.4pJ/b (32, 8) LDPC decoder with time-domain analog and digital mixed-signal processing. |
Year | DOI | Venue |
|---|---|---|
2013 | 10.1109/ISSCC.2013.6487796 | ISSCC |
Keywords | Field | DocType |
CMOS analogue integrated circuits,arithmetic,circuit complexity,integrated circuit design,mixed analogue-digital integrated circuits,parity check codes,time-domain analysis,wires (electric),ADC/DAC,CMOS,LDPC decoder,TDMixed signal processing,arithmetic operation,design complexity,digital system,interface circuit overhead,logical operation,low-density parity-check decoder,size 65 nm,time-domain analog and digital mixed-signal processing,voltage-domain analog computation,wire | Signal processing,Digital signal processing,Analog device,Analog multiplier,Computer science,Low-density parity-check code,CMOS,Electronic engineering,Mixed-signal integrated circuit,Analog signal | Conference |
Volume | ISSN | Citations |
56 | 0193-6530 | 5 |
PageRank | References | Authors |
0.76 | 5 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Daisuke Miyashita | 1 | 72 | 9.99 |
| Ryo Yamaki | 2 | 44 | 4.62 |
| Kazunori Hashiyoshi | 3 | 5 | 0.76 |
| Hiroyuki Kobayashi | 4 | 7 | 1.90 |
| Shouhei Kousai | 5 | 127 | 18.37 |
| Yukihito Oowaki | 6 | 38 | 6.51 |
| Yasuo Unekawa | 7 | 32 | 5.89 |