Name
Abstract | ||
|---|---|---|
Shorts and opens are two major kind of defects that are most likely to occur in Very Large Scale Integrated Circuits. In modern Integrated Circuit devices these defects must be considered not only at gate-level but also at transistor level. In this paper, we propose a method for generating test vectors that targets both transistor shorts (tr-shorts) and transistor opens (tr-opens). Since two consecutive test vectors need to be applied in order to detect tr-opens, we assume launch on capture (LOC) test application mechanism. This makes it possible to detect delay type defects. Further, the proposed method employs existing stuck-at test generation tools thus requiring no change in the design and development flow and development of no new tools is needed. Experimental results for benchmark circuits demonstrate the effectiveness of the proposed method by providing 100% fault efficiency while the test set size is still moderate. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1587/transfun.E92.A.3128 | IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES |
Keywords | Field | DocType |
test generation, transistor defects, stuck-at tests, defect coverage | Automatic test pattern generation,Electronic engineering,Theoretical computer science,Very large scale integrated circuits,Test compression,Transistor,Electronic circuit,Integrated circuit,Electrical engineering,Mathematics,Test set | Journal |
Volume | Issue | ISSN |
E92A | 12 | 0916-8508 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
5 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Kewal K. Saluja | 2 | 1483 | 141.49 |
| Hiroshi Takahashi | 3 | 148 | 24.32 |
| Shin-ya Kobayashi | 4 | 38 | 8.60 |
| Yuzo Takamatsu | 5 | 150 | 27.40 |