Name
Title | ||
|---|---|---|
Silicon-photonic network architectures for scalable, power-efficient multi-chip systems |
Abstract | ||
|---|---|---|
Scaling trends of logic, memories, and interconnect networks lead towards dense many-core chips. Unfortunately, process yields and reticle sizes limit the scalability of large single-chip systems. Multi-chip systems break free of these areal limits, but in turn require enormous chip-to-chip bandwidth. The "macrochip" concept presented here integrates multiple many-core processor chips in a single package with silicon-photonic interconnects. This design enables a multi-chip system to approach the performance of a single large die. In this paper we propose three silicon-photonic network designs that provide low-power, high-bandwidth inter-die communication: a static wavelength-routed point-to-point network, a "two-phase" arbitrated network, and a limited-connectivity point-to-point network. We also adapt two existing intra-chip silicon-photonic interconnects: a token-ring-based crossbar and a circuit-switched torus. We simulate a 64-die, 512-core cache-coherent macrochip using all of the above networks with synthetic kernels, and kernels from Splash-2 and PARSEC. We evaluate the networks on performance, optical power and complexity. Despite a narrow data-path width compared to the token-ring or torus, the point-to-point performs 3.3x and 3.9x better respectively. We show that the point-to-point is over 10x more power-efficient than the other networks. We also show that, contrary to electronic network designs, a point-to-point network has the lowest design complexity for an inter-chip silicon-photonic network. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1145/1815961.1815977 | Proceedings of the 40th Annual International Symposium on Computer Architecture |
Keywords | Field | DocType |
circuit switched,cache coherence,network architecture,network design,power efficiency,silicon photonics,point to point,nanophotonics,chip | Computer architecture,Parsec,Computer science,Parallel computing,Network architecture,Real-time computing,Chip,Bandwidth (signal processing),Silicon photonics,Interconnection,Crossbar switch,Scalability | Conference |
Volume | Issue | ISSN |
38 | 3 | 0163-5964 |
Citations | PageRank | References |
42 | 1.75 | 19 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Pranay Koka | 1 | 112 | 6.81 |
| Michael O. McCracken | 2 | 106 | 5.54 |
| Herb Schwetman | 3 | 375 | 87.15 |
| Xuezhe Zheng | 4 | 169 | 15.89 |
| Ron Ho | 5 | 633 | 47.76 |
| Ashok V. Krishnamoorthy | 6 | 186 | 23.91 |