Name
Abstract | ||
|---|---|---|
To improve the performance and power-consumption of the system-on-chip (SoC), the software processes are often converted to the hardware. However, to extract the performance of the hardware as much as possible, the memory access must be improved. In addition, the development period of the hardware has to be reduced because the life-cycle of SoC is commonly short. This paper proposes a design-level hardware architecture (semi-programmable hardware: SPHW) which is inserted onto the pass from C to hardware. On the SPHW, the memory accesses and buffers are realized by the software programming and parameters respectively. By using the SPHW you can easily develop the data processing hardware containing the efficient memory access controller at C-level abstraction. Compared with the conventional cases, the SPHW can reduce the development time significantly. The experimental result also shows that you can employ the SPHW as the final product if the memory access latency is hidden enough. |
Year | DOI | Venue |
|---|---|---|
2010 | 10.1007/978-3-642-12165-4_39 | ICCSA |
Keywords | Field | DocType |
software programming,efficient memory access controller,design-level hardware architecture,development period,efficient hardware architecture,memory access latency,c program,memory access,semi-programmable hardware,development time,software process,data processing hardware,system on chip,life cycle,data processing,hardware architecture | Desktop and mobile Architecture for System Hardware,Uniform memory access,Hardware compatibility list,Computer science,Hardware register,Hardware acceleration,Memory address,Computer hardware,Multi-channel memory architecture,Hardware architecture | Conference |
Volume | ISSN | ISBN |
6017 | 0302-9743 | 3-642-12164-0 |
Citations | PageRank | References |
0 | 0.34 | 7 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Akira Yamawaki | 1 | 17 | 9.36 |
| Seiichi Serikawa | 2 | 540 | 38.54 |
| Masahiko Iwane | 3 | 13 | 3.79 |