Name
Abstract | ||
|---|---|---|
In a clustered programmable-reconfigurable processor, multiple programmable processors and blocks of reconfigurable logic communicate through a register-based communication mechanism, which reduces the impact of wire delay on clock cycle time. In this paper, we present a circuit-level design for the reconfigurable clusters used on the Amalgam programmable-reconfigurable processor. We outline our interleaved reconfigurable array design, which provides high bandwidth to and from the register file without requiring large amounts of register control logic. We characterize the latency of operations in our array, and present results that show the impact that this latency has on overall system performance in a range of fabrication processes. Finally, we present a pipelining scheme that enables the array to operate at clock rates closer to those of programmable processors and allows for better scaling in future technologies. |
Year | DOI | Venue |
|---|---|---|
2004 | 10.1145/968280.968309 | FPGA |
Keywords | Field | DocType |
reconfigurable logic,clock cycle time,circuit-level design,multiple programmable processor,present result,interleaved reconfigurable array design,amalgam programmable-reconfigurable processor,reconfigurable cluster,clock rate,programmable processor,reconfigurable unit,register file,system performance,cycle time,fpga | Pipeline (computing),Computer science,Latency (engineering),Parallel computing,Field-programmable gate array,Register file,Real-time computing,Clock cycle time,Control logic,Programmable logic device,Embedded system,High bandwidth | Conference |
ISBN | Citations | PageRank |
1-58113-829-6 | 4 | 0.42 |
References | Authors | |
10 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Richard B. Kujoth | 1 | 6 | 1.17 |
| Chi-Wei Wang | 2 | 26 | 4.37 |
| Derek B. Gottlieb | 3 | 9 | 2.73 |
| Jeffrey J. Cook | 4 | 110 | 7.45 |
| Nicholas P. Carter | 5 | 349 | 33.84 |