Jeffrey J. Cook - Citegraph

Author Info

Name	Affiliation	Papers
JEFFREY J. COOK	Univ Illinois, Dept Comp Sci, 1304 W Springfield Ave, Urbana, IL 61801 USA	13
Collaborators	Citations	PageRank
27	110	7.45
Referers	Referees	References
332	246	105

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100332

Publications (13 rows)

Collaborators (27 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
WRPN: Wide Reduced-Precision Networks.	0	0.34	2018
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC(Abstract Only).	0	0.34	2018
In-Package Domain-Specific ASICs for Intel® Stratix® 10 FPGAs: A Case Study of Accelerating Deep Learning Using TensorTile ASIC	0	0.34	2018
WRPN: Wide Reduced-Precision Networks.	20	0.73	2017
WRPN: Training and Inference using Wide Reduced-Precision Networks.	2	0.37	2017
Blueshift: Designing processors for timing speculation from the ground up	57	2.17	2009
A characterization of instruction-level error derating and its implications for error detection	22	0.78	2008
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor	0	0.34	2007
Exploiting pipelining to tolerate wire delays in a programmable-reconfigurable processor	2	0.41	2005
A reconfigurable unit for a clustered programmable-reconfigurable processor	4	0.42	2004
Mapping computation kernels to clustered programmable-reconfigurable processors	0	0.34	2003
Mapping Algorithms to the Amalgam Programmable-Reconfigurable Processor	0	0.34	2002
The Design of the Amalgam Reconfigurable Cluster	3	0.55	2002

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