Name
Abstract | ||
|---|---|---|
The design of MultiProcessor Systems-on-Chip (MPSoC) emphasizes intellectual-property (IP)-based communication-centric approaches. Therefore, for the optimization of the MPSoC interconnect, the designer must develop traffic models that realistically capture the application behavior as executing on the IP core. In this paper, we introduce a Reactive IP Emulator (RIPE) that enables an effective emulation of the IP-core behavior in multiple environments, including bit- and cycle-true simulation. The RIPE is built as a multithreaded abstract instruction-set processor, and it can generate reactive traffic patterns. We compare the RIPE models with cycle-true functional simulation of complex application behavior (task-synchronization, multitasking, and input/output operations). Our results demonstrate high-accuracy and significant speedups. Furthermore, via a case study, we show the potential use of the RIPE in a design-space-exploration context. |
Year | DOI | Venue |
|---|---|---|
2008 | 10.1109/TCAD.2007.906990 | IEEE Trans. on CAD of Integrated Circuits and Systems |
Keywords | DocType | Volume |
IP core,application behavior,IP-core behavior,complex application behavior,RIPE model,Cycle-True IP Emulator,reactive traffic pattern,MPSoC Exploration,cycle-true simulation,cycle-true functional simulation,traffic model,Reactive IP Emulator | Journal | 27 |
Issue | ISSN | Citations |
1 | 0278-0070 | 5 |
PageRank | References | Authors |
0.58 | 17 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| S. Mahadevan | 1 | 843 | 36.64 |
| F. Angiolini | 2 | 144 | 8.26 |
| Sparso, J. | 3 | 133 | 104.88 |
| Luca Benini | 4 | 13116 | 1188.49 |
| Jan Madsen | 5 | 576 | 56.90 |