Name
Title | ||
|---|---|---|
Design of on-line testing for SoC with IEEE P1500 compliant cores using reconfigurable hardware and scan shift |
Abstract | ||
|---|---|---|
In this paper, a new design for online testing of system on a chip (SoC) is presented. The proposed method is based on usage of the available IEEE P1500 architecture and a small embedded FPGA core. Our method has a little additional routing overhead of the SoC, which keeps its performance much higher than conventional approaches. The design of this method is easy and it does not make a burden on the system designer. The error latency has an order of only few minutes in worst case scenario. We present the hardware implementation of this method and evaluate its performances. |
Year | DOI | Venue |
|---|---|---|
2005 | 10.1109/IOLTS.2005.22 | IOLTS |
Keywords | Field | DocType |
small embedded fpga core,ieee p1500 compliant,reconfigurable hardware,new design,conventional approach,system on chip,ieee p1500 compliant cores,soc,hardware implementation,on-line testing,error latency,additional routing overhead,reconfigurable architectures,p1500 architecture,available ieee,online testing,system-on-chip,embedded fpga core,ieee standards,scan shift,embedded systems,field programmable gate arrays,degradation,system design,routing,indium tin oxide,fault detection,system on a chip,hardware | System on a chip,Latency (engineering),Fault detection and isolation,Computer science,Field-programmable gate array,Electronic engineering,Real-time computing,Worst-case scenario,Reconfigurable computing,Embedded system | Conference |
ISBN | Citations | PageRank |
0-7695-2406-0 | 3 | 0.40 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kentaroh Katoh | 1 | 34 | 6.64 |
| Abderrahim Doumar | 2 | 109 | 8.61 |
| Hideo Ito | 3 | 100 | 17.45 |