Paper Info
Title
System-Level Comparison Of Power Delivery Design For 2d And 3d Ics
Abstract
Three-dimensional integrated circuits (IC) promise high bandwidth, low latency, low device power, and a small form factor. Increased device density and asymmetrical packaging, however, render 3D power delivery design a challenge. In this paper, we provide a system-level comparison of power delivery for 2D and 3D ICs. We investigate various techniques that can impact the quality of power delivery in 3D ICs. These include through-silicon via (TSV) size and spacing, controlled collapse chip connection (C4) spacing, and a combination of dedicated and shared power delivery. Our evaluation system is composed of quad-core chip multiprocessor, memory, and accelerator engine. Each of these modules is running representative SPEC benchmark traces. Our findings are practical and provide clear guidelines for 3D power delivery optimization. More importantly, we show that it is possible to achieve 2D-like or even better power quality by increasing C4 granularity and selecting suitable TSV size and spacing.
Year
DOI
Venue
2009
10.1109/3DIC.2009.5306539
2009 IEEE INTERNATIONAL CONFERENCE ON 3D SYSTEMS INTEGRATION
Keywords
Field
DocType
load flow analysis,through silicon via,power electronics,benchmark testing,system on a chip,low latency,three dimensional,integrated circuit design,silicon,form factor,chip,integrated circuit
Power-flow study,System on a chip,Small form factor,Electronic engineering,Integrated circuit design,Power electronics,Latency (engineering),Engineering,Integrated circuit,Benchmark (computing),Embedded system
Conference
ISSN
Citations 
PageRank 
2164-0157
18
1.09
References 
Authors
8
3
Name
Order
Citations
PageRank
Nauman H. Khan1584.21
Syed M. Alam217620.47
Soha Hassoun3535241.27