Name
Abstract | ||
|---|---|---|
This paper addresses the problem of simultaneous presence of multiple faults consisting of clock delay and gate transitions faults. The conditions of detecting a target multiple fault are converted into those for detecting a single stuck-at fault by adding some logic during the ATPG process. Experimental results show the effectiveness of our method by achieving nearly 100% fault efficiency. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/ETS.2011.27 | European Test Symposium |
Keywords | Field | DocType |
atpg process,single stuck-at fault,clock delay faults testing,multiple fault,gate transitions fault,simultaneous presence,target multiple fault,clock delay,fault efficiency,benchmark testing,automatic test pattern generation,logic gates,stuck at fault | Stuck-at fault,Automatic test pattern generation,Object detection,Logic gate,Computer science,Logic testing,Real-time computing,Electronic engineering,Benchmark (computing),AND gate,Fault indicator | Conference |
ISSN | Citations | PageRank |
1530-1877 | 2 | 0.46 |
References | Authors | |
1 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Hiroshi Takahashi | 2 | 148 | 24.32 |
| Shin-ya Kobayashi | 3 | 38 | 8.60 |
| Kewal K. Saluja | 4 | 1483 | 141.49 |