Paper Info
Title
A Low-Power DSP for Wireless Communications
Abstract
This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture-Signal processing On Demand Architecture (SODA)-which is a four-processor, 32-lane SIMD machine that was optimized for WCDMA 2 Mbps and IEEE 802.11a. SODA has several shortcomings including large register file power, wasted cycles for data alignment, etc., and cannot satisfy the higher throughput and lower power requirements of emerging standards. We propose SODA-II, which addresses these problems by deploying the following schemes: operation chaining, pipelined execution of SIMD units, staggered memory access, and multicycling of computation units. Operation chaining involves chaining the primitive instructions, thereby eliminating unnecessary register file accesses and saving power. Pipelined execution of the vector instructions through the SIMD units improves the system throughput. Staggered execution of computation units helps simplify the data alignment networks. It is implemented in conjunction with multicycling so that the computation units are busy most of the time. The proposed architecture is evaluated with an in-house architecture emulator which uses component-level area and power models built with Synopsys and Artisan tools. Our results show that for WCDMA 2 Mbps, the proposed architecture uses two processors and consumes only 120 mW while SODA uses four processors and consumes 210 mW when implemented in 0.13-μm technology and clocked at 300 MHz.
Year
DOI
Venue
2010
10.1109/TVLSI.2009.2023547
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Keywords
Field
DocType
soda-ii,low-power dsp,parallel processing,wireless communications,wcdma,large register file power,register file accesses,inhouse architecture emulator,synopsys tool,simd machine,lower power requirement,signal processing on demand architecture,telecommunication terminals,staggered memory access,proposed architecture,data alignment networks,operation chaining,wireless communication,digital signal processing (dp),power 120 mw,power model,digital signal processing chips,power models,software-defined radio (sdr),code division multiple access,bit rate 2 mbit/s,vector instructions,baseband processing,low power,power 210 mw,programmable,in-house architecture emulator,frequency 300 mhz,component-level area,wireless terminals,simd unit,simd,baseband processor,earlier architecture,computation unit,pipelined execution,size 0.13 mum,wireless lan,artisan tool,simd units,digital signal processor,ieee 802.11a,register file,software defined radio,satisfiability,registers,indexing terms,digital signal processing,computer architecture,kernel,baseband,ieee 802 11a,high throughput,throughput
Digital signal processing,Chaining,Computer science,Digital signal processor,SIMD,Register file,Baseband processor,Real-time computing,Electronic engineering,Data structure alignment,Low-power electronics,Embedded system
Journal
Volume
Issue
ISSN
18
9
1063-8210
Citations 
PageRank 
References 
14
1.06
9
Authors
3
Name
Order
Citations
PageRank
Hyun-Seok Lee124825.22
Chaitali Chakrabarti21978184.17
Trevor Mudge36139659.74