Name
Abstract | ||
|---|---|---|
In this paper, we present a novel hybrid multiplier architecture that has the regularity of linear array multipliers and the performance of tree multipliers and is highly scalable to higher-order multiplication. This multiplier topology is highly conducive for an electronic design automation (EDA) tool based implementation. A 32-bit version of this multiplier has been implemented using a standard ASIC design methodology and one variation of the standard design methodology in a 0.25μm technology. This 32-bit multiplier has a latency of 3.56ns. |
Year | DOI | Venue |
|---|---|---|
2003 | 10.1145/764808.764871 | ACM Great Lakes Symposium on VLSI |
Keywords | Field | DocType |
standard asic design methodology,linear array multiplier,multiplier topology,32-bit version,standard design methodology,m technology,32-bit multiplier,electronic design automation,novel hybrid multiplier architecture,tree multiplier,novel 32-bit scalable multiplier,higher order,architecture,design methodology,multiplier | 32-bit,Computer architecture,Computer science,Latency (engineering),Electronic engineering,Design methods,Application-specific integrated circuit,Multiplier (economics),Multiplication,Electronic design automation,Scalability | Conference |
ISBN | Citations | PageRank |
1-58113-677-3 | 2 | 0.44 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yeshwant Kolla | 1 | 2 | 0.44 |
| Yong-bin Kim | 2 | 338 | 55.72 |
| John B. Carter | 3 | 1785 | 162.82 |