Name
Abstract | ||
|---|---|---|
This paper presents diagnosis methods for bridging faults between a clock line and a gate signal line. Scan-based simulation methods are applied while assuming that only scan-based flush tests are used. In view of the fact that initial states play an important role, we consider two possible scenarios: 1) all flip-flops are assumed to be reset table, and 2) flip-flops are not reset table. In order to handle unknown states due to the non-reset table flip-flops, we introduce heuristic techniques. The effectiveness of the proposed methods are evaluated by the experimental results for benchmark circuits. |
Year | DOI | Venue |
|---|---|---|
2012 | 10.1109/PRDC.2012.15 | Dependable Computing |
Keywords | Field | DocType |
bridging faults,gate signal line,clock lines,heuristic technique,flush test,benchmark circuit,reset table,diagnosis method,non-reset table flip-flop,clock line,scan-based simulation method,benchmark testing,logic gates | Logic gate,Heuristic,Computer science,Bridging (networking),Real-time computing,Electronic circuit,Signal lines,Benchmark (computing) | Conference |
ISBN | Citations | PageRank |
978-0-7695-4885-2 | 0 | 0.34 |
References | Authors | |
8 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yoshinobu Higami | 1 | 140 | 27.24 |
| Hiroshi Takahashi | 2 | 148 | 24.32 |
| Shin-ya Kobayashi | 3 | 38 | 8.60 |
| Kewal K. Saluja | 4 | 1483 | 141.49 |