Name
Abstract | ||
|---|---|---|
This paper presents mathematical foundations for the design of a memory controller subcomponent that helps to bridge the processor/memory performance gap for applications with strided access patterns. The Parallel Vector Access (PVA) unit exploits the regularity of vectors or streams to access them efficiently in parallel on a multi-bank SDRAM memory system. The PVA unit performs scatter/gather operations so that only the elements accessed by the application are transmitted across the system bus. Vector operations are broadcast in parallel to all memory banks, each of which implements an efficient algorithm to determine which vector elements it holds. Earlier performance evaluations have demonstrated that our PVA implementation loads elements up to 32.8 times faster than a conventional memory system and 3.3 times faster than a pipelined vector unit, without hurting the performance of normal cache-line fills. Here we present the underlying PVA algorithms for both word interleaved and cache-line inter-leaved memory systems. |
Year | DOI | Venue |
|---|---|---|
2000 | 10.1145/341800.341819 | SPAA |
Keywords | Field | DocType |
parallel vector access memory,cache-line inter-leaved memory system,multi-bank sdram memory system,memory controller subcomponent,conventional memory system,memory performance gap,pva unit,underlying pva algorithm,pva implementation,memory bank,algorithmic foundation,earlier performance evaluation | Registered memory,Semiconductor memory,Interleaved memory,Uniform memory access,Shared memory,Computer science,Parallel computing,Memory map,Computer hardware,Computer memory,Memory controller,Distributed computing | Conference |
ISBN | Citations | PageRank |
1-58113-185-2 | 6 | 0.45 |
References | Authors | |
15 | 4 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Binu K. Mathew | 1 | 166 | 12.25 |
| Sally A. Mckee | 2 | 1928 | 152.59 |
| John B. Carter | 3 | 1785 | 162.82 |
| Al Davis | 4 | 986 | 54.47 |