Name
Abstract | ||
|---|---|---|
As semiconductor technologies progress, testing of small delay defects are becoming more important for SoCs. However, fault diagnosis of small delay defects has not been developed. We propose a novel timing-aware method for diagnosing small delay defects with a small computation cost using gate delay fault simulation with the minimum detectable delay, as introduced in the statistical delay quality model. The experimental results show that the proposed method is capable of identifying fault locations for small delay defects with a small computation cost. |
Year | DOI | Venue |
|---|---|---|
2007 | 10.1109/DFT.2007.30 | DFT |
Keywords | Field | DocType |
fault diagnosis,small delay defects,fault location,small computation cost,timing-aware diagnosis,novel timing-aware method,minimum detectable delay,small delay defect,statistical delay quality model,gate delay fault simulation,soc,system on chip | System on a chip,Semiconductor technology,Computer science,Electronic engineering,Real-time computing,Elmore delay,Computation | Conference |
ISSN | ISBN | Citations |
1550-5774 | 0-7695-2885-6 | 4 |
PageRank | References | Authors |
0.45 | 9 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Takashi Aikyo | 1 | 93 | 11.46 |
| Hiroshi Takahashi | 2 | 148 | 24.32 |
| Yoshinobu Higami | 3 | 140 | 27.24 |
| junichi ootsu | 4 | 4 | 0.45 |
| kyohei ono | 5 | 4 | 0.45 |
| Yuzo Takamatsu | 6 | 150 | 27.40 |