Paper Info
Title
Processing assessment and adhesion evaluation of copper through-silicon vias (TSVs) for three-dimensional stacked-integrated circuit (3D-SIC) architectures
Abstract
Through-silicon vias (TSVs) are critical components in most 3D architectures. In this paper, fully filled cylindrical Cu TSVs with a diameter of 5μm and a depth of 25μm were used to demonstrate quantitative assessment of the fabrication process and the interfacial adhesion of the TSVs. For TSV fabrication, the coverage of barrier and seed layers was respectively examined through dilute HF dipping and copper decoration plating. The adhesion between the TSVs and the substrate, which is of great importance for the functionality and long-term reliability of the TSVs, was characterized by four-point bending in combination with fractographic analysis. The scanning electron microscopic (SEM) images of the fracture indicate that the top of a TSV has better adhesion than the rest. This can be due to the non-uniformity of sidewall roughness and barrier thickness. A degradation of adhesion at the top was observed after thermal cycling tests, which seems to confirm the hypothesis of the influence of the roughness. These reliability tests should be taken as additional criteria for the assessment of TSV properties.
Year
DOI
Venue
2010
10.1016/j.microrel.2010.07.019
Microelectronics Reliability
Keywords
Field
DocType
scanning electron microscope,thermal cycling,copper,three dimensional,through silicon via,integrated circuit
Composite material,Engineering drawing,Silicon carbide,Electronic engineering,Barrier layer,Adhesion,Temperature cycling,Surface finish,Engineering,Integrated circuit,Fabrication,Silicon
Journal
Volume
Issue
ISSN
50
9
0026-2714
Citations 
PageRank 
References 
5
1.09
1
Authors
9
Name
Order
Citations
PageRank
Yangyuan Wang114223.85
R. Labie251.09
F. Ling351.09
C. Zhao452.11
A. Radisic551.09
J. Van Olmen651.09
Y. Travaly751.43
B. Verlinden882.53
I. De Wolf9177.89