Paper Info
Title
Genetic Algorithm-Based Methodology for Pattern Recognition Hardware
Abstract
In this paper, we propose a new logic circuit design methodology for pattern recognition chips using the genetic algorithms. In the proposed design methodology, pattern data are transformed into the truth tables and the truth tables are generalized to adapt the unknown pattern data. The genetic algorithm is used to choose the generalization operators. The generalized, or evolved truth tables are then synthesized to logic circuits. Because of this data direct implementation approach, no floating point numerical circuits are required and the intrinsic parallelism in the data is embedded into the circuits. Consequently, high speed recognition systems can be realized with acceptable small circuit size. We have applied this methodology to the face image recognition and the sonar spectrum recognition tasks, and implemented them onto the developed FPGA-based reconfigurable pattern recognition board. The developed system demonstrates high recognition accuracy and much higher processing speed than the conventional approaches.
Year
DOI
Venue
2000
10.1007/3-540-46406-9_26
ICES
Keywords
Field
DocType
pattern recognition chip,sonar spectrum recognition task,pattern data,genetic algorithm-based methodology,data direct implementation approach,face image recognition,genetic algorithm,pattern recognition hardware,truth table,high recognition accuracy,high speed recognition system,fpga-based reconfigurable pattern recognition,pattern recognition
Logic gate,Pattern recognition,Floating point,Computer science,Field-programmable gate array,Sonar,Truth table,Feature (machine learning),Artificial intelligence,Electronic circuit,Genetic algorithm
Conference
ISBN
Citations 
PageRank 
3-540-67338-5
15
1.02
References 
Authors
4
4
Name
Order
Citations
PageRank
Moritoshi Yasunaga117833.03
Taro Nakamura2151.70
Ikuo Yoshihara312018.53
Jung H. Kim47614.00