Paper Info
Title
A built-in self-test scheme for the post-bond test of TSVs in 3D ICs
Abstract
Three-dimensional (3D) integration using through silicon via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. A 3D IC including multiple dies connected with TSVs offers many benefits over current 2D ICs. However, the testing of 3D ICs is much more difficult than that of 2D ICs. In this paper, we propose a cost-effective built-in self-test circuit (BIST) to test TSVs of a 3D IC. The BIST scheme, arranging the TSVs into arrays similar to memory, has the features of low test/diagnosis time and low silicon area cost. Simulation results show that the area overhead of the BIST circuit implemented with 0.18μm CMOS technology for a 16×32 TSV array in which each TSV cell size is 45μm2 is 2.24%. Also, the BIST needs only 130 clock cycles to test the TSV array with stuck-at faults. In comparison with the IEEE 1500-based test approach, the BIST scheme can achieve 85.2% area cost and 93.6% test time reduction.
Year
DOI
Venue
2011
10.1109/VTS.2011.5783749
VTS
Keywords
DocType
ISSN
cmos integrated circuits,integrated circuit testing,three-dimensional integrated circuits,tsv array,built-in self test,cmos technology,size 0.18 mum,bist,built-in self-test scheme,post-bond test,ieee 1500-based test approach,three-dimensional integrated circuit,3d ic,2d ic,logic gates,socs,design,through silicon via,optimization,three dimensional integrated circuit,cost effectiveness
Conference
1093-0167
ISBN
Citations 
PageRank 
978-1-61284-657-6
31
1.45
References 
Authors
17
6
Name
Order
Citations
PageRank
Yu-Jen Huang115414.91
Jin-Fu Li266259.17
Ji-Jan Chen31169.34
Ding-Ming Kwai452146.85
Yung-Fa Chou524423.76
Wu, Cheng-Wen61843170.44