Name
Abstract | ||
|---|---|---|
Coarse grain reconfigurable array architectures have become increasingly popular due to their flexibility, scalability and performance. However, the mapping of programs on these architectures is characterized by huge complexity. This work presents a new mapping methodology for effectively mapping applications on coarse grained reconfigurable arrays. The core of this methodology comprises of the scheduling and register allocation phases performed, for the first time in the case of CGRAs, in a single step. Additionally, modulo scheduling with backtracking capability is incorporated in this scheme. The main contribution of this work includes a novel technique for minimizing the memory bandwidth bottleneck, a new priority scheme and a new set of heuristics which target on the maximization of the Instruction Level Parallelism by efficiently managing the architecture's resources. The overall approach is retargetable with respect to a parametric architecture template modelling a large number of architecture alternatives and it has been automated with a prototype tool which permits experimental exploration. The experimental results showed that the achieved performance figures are very close to the most effective ones derived from the theoretical study on the architecture's resources and the applications requirements. Moreover, the application of the bandwidth optimization technique lead to a 20-130% increase on operation parallelism. Finally, the experiments quantified the benefit from applying the new priority scheme and heuristics. |
Year | DOI | Venue |
|---|---|---|
2009 | 10.1016/j.micpro.2008.07.002 | Microprocessors and Microsystems - Embedded Hardware Design |
Keywords | Field | DocType |
reconfigurable computing,experimental exploration,applications requirement,new priority scheme,architecture alternative,data reuse,coarse grained reconfigurable arrays,coarse grain reconfigurable array,coarse grained reconfigurable array,new mapping methodology,mapping,new set,resource aware mapping,parametric architecture template,bandwidth optimization technique lead,data bandwidth bottleneck,register allocation,memory bandwidth | Instruction-level parallelism,Bottleneck,Memory bandwidth,Register allocation,Scheduling (computing),Computer science,Parallel computing,Real-time computing,Heuristics,Scalability,Reconfigurable computing | Journal |
Volume | Issue | ISSN |
33 | 2 | Microprocessors and Microsystems |
Citations | PageRank | References |
16 | 0.70 | 23 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Grigorios Dimitroulakos | 1 | 17 | 1.05 |
| Stavros Georgiopoulos | 2 | 16 | 0.70 |
| Michalis D. Galanis | 3 | 94 | 15.60 |
| Costas E Goutis | 4 | 186 | 25.76 |