Name
Abstract | ||
|---|---|---|
Two alternative BIST schemes are proposed for structural testing of pipelined Analog-to-Digital Converters (ADC). They are oriented to fault detection in the converter stages rather than to measure the whole ADC electrical performance parameters. The operational principle of both strategies relies on testing every ADC stage reconfigured as an A/D-D/A block and applying as input a simple DC stimuli set which is easily obtained, without strong precision requirements, by a resistive network. The main differences between both strategies relate to the way the output response is evaluated. In the BIST#1 scheme, analog and digital outputs are compared with reference levels generated with a reference D/A converter and a counter. In the BIST#2 strategy, only digital outputs are available and they are compared with fault-free values previously stored in an on-chip register. The new techniques are intended to be used in pipelined converters of an arbitrary number of conversion stages and with a digital self-correction mechanism. |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1023/A:1012747017838 | J. Electronic Testing |
Keywords | Field | DocType |
BIST,mixed-signal IC test,testable ADC,design for test,pipelined analog to digital converters | Design for testing,Structural testing,Fault detection and isolation,Computer science,Resistive touchscreen,Delta-sigma modulation,To digital converter,Electronic engineering,Real-time computing,Converters,Successive approximation ADC | Journal |
Volume | Issue | ISSN |
17 | 5 | 1573-0727 |
Citations | PageRank | References |
3 | 0.45 | 6 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Eduardo J. Peralías | 1 | 58 | 16.71 |
| Adoración Rueda | 2 | 275 | 40.01 |
| José L. Huertas | 3 | 159 | 18.91 |