Eduardo J. Peralías

Author Info

Name	Affiliation	Papers
EDUARDO J. PERALÍAS	Centro Nacional de Microelectrónica (CNM), University of Seville, Avda. Reina Mercedes s/n. Edificio CICA. 41012-Sevilla, Spain	36
Collaborators	Citations	PageRank
38	58	16.71
Referers	Referees	References
149	379	138

Search Limit

100379

Publications (36 rows)

Collaborators (38 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
Digital Non-Linearity Calibration for ADCs With Redundancy Using a New LUT Approach	0	0.34	2021
Calibration of Capacitor Mismatch and Static Comparator Offset in SAR ADC with Digital Redundancy	0	0.34	2020
Fast Simulation of Non-Linear Circuits using Semi-Analytical Solutions Based on the Matrix Exponential	0	0.34	2020
Fast Adaptive Comparator Offset Calibration In Pipeline Adc With Self-Repairing Thermometer To Binary Encoder	0	0.34	2019
Black-Box Calibration for ADCs With Hard Nonlinear Errors Using a Novel INL-Based Additive Code: A Pipeline ADC Case Study	0	0.34	2017
Fast Background Calibration of Sampling Timing Skew in SHA-Less Pipeline ADCs.	0	0.34	2017
On the limits of machine learning-based test: A calibrated mixed-signal system case study.	0	0.34	2017
Semi-empirical RF MOST model for CMOS 65 nm technologies: Theory, extraction method and validation.	0	0.34	2016
INL systematic reduced-test technique for Pipeline ADCs	2	0.70	2014
Closed-loop simulation method for evaluation of static offset in discrete-time comparators	0	0.34	2014
Analysis of steady-state common-mode response in differential LC-VCOs.	0	0.34	2012
Self-biased input common-mode generation for improving dynamic range and yield in inverter-based filters.	0	0.34	2012
2.4-GHz single-ended input low-power low-voltage active front-end for ZigBee applications in 90 nm CMOS.	3	0.61	2011
Blind Adaptive Estimation of Integral Nonlinear Errors in ADCs Using Arbitrary Input Stimulus	3	0.53	2011
Power optimization of CMOS programmable gain amplifiers with high dynamic range and common-mode feed-forward circuit.	0	0.34	2010
A fully differential monolithic 2.4GHZ PA for IEEE 802.15.4 based on efficiency design flow.	0	0.34	2010
On Chopper Effects in Discrete-Time SigmaDelta Modulators.	0	0.34	2010
ADC non-linearity low-cost test through a simplified Double-Histogram method	3	0.44	2010
A 1.2V 5.14mW quadrature frequency synthesizer in 90nm CMOS technology for 2.4GHz ZigBee applications.	0	0.34	2008
Simple evaluation of the nonlinearity signature of an ADC using a spectral approach	5	0.51	2008
Improved Background Algorithms for Pipeline ADC Full Calibration	1	0.41	2007
Novel swapping technique for background calibration of capacitor mismatching in pipeline ADCS	0	0.34	2007
Statistical analysis of a background correlation-based technique for full calibration of pipeline ADCs	1	0.37	2006
Digital self-tuning technique for continuous-time filters.	0	0.34	2005
Digital Background Gain Error Correction in Pipeline ADCs	2	0.44	2004
Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages	4	0.57	2003
A Mixed-Signal Design Reuse Methodology Based on Parametric Behavioural Models with Non-Ideal Effects	5	0.64	2002
Self-Testable Pipelined ADC with Low Hardware Overhead	1	0.43	2001
Structural testing of pipelined analog to digital converters	9	1.06	2001
Analog/mixed-signal IP modeling for design reuse	3	0.79	2001
New BIST Schemes for Structural Testing of Pipelined Analog to Digital Converters	3	0.45	2001
An Application of Self-Timed Circuits to the Reduction of Switching Noise in Analog-Digital Circuits	1	0.38	2000
An approach to realistic fault prediction and layout design for testability in analog circuits	0	0.34	1998
SWITTEST: automatic switch-level fault simulation and test evaluation of switched-capacitor systems	7	1.35	1997
A DFT Technique for Analog-to-Digital Converters with digital correction	3	0.54	1997
Statistical behavioral modeling and characterization of A/D converters	2	0.40	1995