Name
Title | ||
|---|---|---|
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores |
Year | DOI | Venue |
|---|---|---|
2001 | 10.1109/ISCAS.2001.922318 | ISCAS (4) |
Keywords | Field | DocType |
vlsi,power generation,embedded systems,very large scale integration,jitter,phase locked loops,standard cell,vlsi design,energy management,circuits | Clock generator,Computer science,Clock domain crossing,Microprocessor,Electronic engineering,Clock skew,Digital clock,Jitter,Digital clock manager,Very-large-scale integration | Conference |
Citations | PageRank | References |
1 | 0.38 | 2 |
Authors | ||
2 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mauro Olivieri | 1 | 385 | 36.09 |
| A. Trifiletti | 2 | 433 | 63.29 |