| Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications | 0 | 0.34 | 2021 |
| Delay models and design guidelines for MCML gates with resistor or PMOS load | 0 | 0.34 | 2020 |
| 0.6-V Cmos Cascode Ota With Complementary Gate-Driven Gain-Boosting And Forward Body Bias | 1 | 0.37 | 2020 |
| High-speed AWG exploiting parallel time interleaved DAC cores | 0 | 0.34 | 2020 |
| Low-Power Class-Ab 4(Th)-Order Low-Pass Filter Based On Current Conveyors With Dynamic Mismatch Compensation Of Biasing Errors | 0 | 0.34 | 2020 |
| An Improved Reversed Miller Compensation Technique For Three-Stage Cmos Otas With Double Pole-Zero Cancellation And Almost Single-Pole Frequency Response | 0 | 0.34 | 2020 |
| A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering | 0 | 0.34 | 2020 |
| Area-Efficient Low-Power Bandpass Gm-C Filter for Epileptic Seizure Detection in 130nm CMOS | 0 | 0.34 | 2019 |
| A low-power class-AB Gm-C biquad stage in CMOS 40nm technology | 0 | 0.34 | 2019 |
| High-Gain, High-Cmrr Class Ab Operational Transconductance Amplifier Based On The Flipped Voltage Follower | 0 | 0.34 | 2019 |
| A Topology of Fully-Differential Class-AB Symmetrical OTA with Improved CMRR | 0 | 0.34 | 2018 |
| New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks. | 0 | 0.34 | 2018 |
| A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering | 0 | 0.34 | 2018 |
| TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results. | 1 | 0.35 | 2018 |
| A Novel Very Low Voltage Topology to implement MCML XOR Gates | 0 | 0.34 | 2018 |
| A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR. | 0 | 0.34 | 2018 |
| Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks. | 2 | 0.36 | 2018 |
| Perfect reconstruction filters for 4-channels time-interleaved ADC affected by mismatches | 0 | 0.34 | 2017 |
| Calibration of Time-Interleaved ADCs via Hermitianity-Preserving Taylor Approximations | 0 | 0.34 | 2017 |
| Multivariate Analysis Exploiting Static Power On Nanoscale Cmos Circuits For Cryptographic Applications | 0 | 0.34 | 2017 |
| Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications. | 3 | 0.42 | 2017 |
| 0.9-V Class-AB Miller OTA in 0.35-µm CMOS With Threshold-Lowered Non-Tailed Differential Pair. | 1 | 0.37 | 2017 |
| Faster, Stabler, and Simpler - A Recursive-Least-Squares Algorithm Exploiting the Frisch-Waugh-Lovell Theorem. | 1 | 0.43 | 2017 |
| Fully Differential Class-AB OTA with Improved CMRR. | 0 | 0.34 | 2017 |
| A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric. | 4 | 0.41 | 2017 |
| The recursive batch least squares filter: An efficient RLS filter for floating-point hardware | 0 | 0.34 | 2017 |
| Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies. | 2 | 0.41 | 2017 |
| Template attacks exploiting static power and application to CMOS lightweight crypto-hardware. | 0 | 0.34 | 2017 |
| On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology | 0 | 0.34 | 2016 |
| Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power | 4 | 0.48 | 2016 |
| CMOS Non-tailed differential pair. | 0 | 0.34 | 2016 |
| Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption | 5 | 0.57 | 2016 |
| A fault-tolerant real-time microcontroller with multiprocessor architecture | 0 | 0.34 | 2016 |
| A shared memory, parameterized and configurable in FPGA, for use in multiprocessor systems | 0 | 0.34 | 2016 |
| A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier | 0 | 0.34 | 2016 |
| Synthesis of anti-aliasing filters for IF receivers | 0 | 0.34 | 2016 |
| High-tuning-range CMOS band-pass IF filter based on a low-Q cascaded biquad optimization technique | 1 | 0.41 | 2015 |
| Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration | 3 | 0.58 | 2015 |
| Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks | 5 | 0.45 | 2015 |
| Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer | 0 | 0.34 | 2014 |
| Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher | 1 | 0.35 | 2014 |
| A Novel Wake-Up Receiver with Addressing Capability for Wireless Sensor Nodes | 10 | 0.58 | 2014 |
| A wideband amplifier topology based on positive capacitive feedback | 1 | 0.41 | 2014 |
| 88- A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors | 7 | 0.61 | 2014 |
| A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family | 3 | 0.37 | 2013 |
| Adaptive Frequency Compensation For Maximum And Constant Bandwidth Feedback Amplifiers | 2 | 0.42 | 2013 |
| Effect of components relative tolerance in the magnitude response of a Gm-C biquad. | 0 | 0.34 | 2013 |
| A logic level countermeasure against CPA side channel attacks on AES | 0 | 0.34 | 2013 |
| Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters | 8 | 0.79 | 2013 |
| Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters. | 5 | 0.58 | 2012 |
