Name
Abstract | ||
|---|---|---|
This paper presents a leakage-efficient instruction TLB (Translation Lookaside Butter) design for embedded processors. The key observation is that when programs enter a physical page, the following instructions tend to be fetched from the same page for a rather long time. Thus, by employing a small storage component which holds the recent address-translation information, the TLB access frequency can be drastically decreased, and the instruction TLB can be turned into the low-leakage mode with the dual voltage supply technique. Based on such a design philosophy, three leakage control policies are proposed to maximize the leakage reduction efficiency. Evaluation results with eight MiBench programs show that the proposed design can reduce the leakage power of the instruction TLB by 50% on average, with only 0.01% performance degradation. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1587/transinf.E94.D.1565 | IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS |
Keywords | Field | DocType |
leakage power, TLB, embedded processor | Computer vision,Computer architecture,Leakage (electronics),Computer science,Voltage,Leakage power,Artificial intelligence,Philosophy of design,Translation lookaside buffer,Embedded system,Access frequency | Journal |
Volume | Issue | ISSN |
E94D | 8 | 1745-1361 |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Lei Zhao | 1 | 22 | 3.05 |
| Hui Xu | 2 | 1 | 1.03 |
| Daisuke Ikebuchi | 3 | 80 | 6.86 |
| Tetsuya Sunata | 4 | 23 | 3.07 |
| Mitaro Namiki | 5 | 97 | 20.69 |
| Hideharu Amano | 6 | 1375 | 210.21 |