Name
Title | ||
|---|---|---|
Low-Power 8gb/S Near-Threshold Serial Link Receivers Using Super-Harmonic Injection Locking In 65nm Cmos |
Abstract | ||
|---|---|---|
A testchip of 8Gb/s forwarded clock serial link receivers is presented. The receiver exploits a novel low-power super-harmonic injection-locked ring oscillator for symmetric multi-phase local clock generation and dekewing. Further power reduction is achieved by designing most the receiver circuits in the near-threshold region of 0.6V supply, with the exception of only the global clock buffer, test buffers and synthesized digital circuits at nominal 1V supply. At architectural level, 1:10 direct demultiplexing rate is chosen as a demonstration of achieving low supply operation by high-parallelism design. Fabricated in 65nm CMOS technology, two receiver prototypes are integrated in this testchip, one without and the other with front S/Hs. Including the amortized power of global clock distribution, they consume 1.3mW and 2mW respectively at 8Gb/s input data rate, which achieve the power efficiency of 0.163mW/Gb/s and 0.25mW/Gb/s. Measurement results show both receivers get BER < 10(-12) across a 20-cm FR4 PCB channel. |
Year | DOI | Venue |
|---|---|---|
2011 | 10.1109/CICC.2011.6055365 | 2011 IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE (CICC) |
Keywords | Field | DocType |
radio receivers,power efficiency,cmos integrated circuits,ring oscillator,digital circuits,injection locking,low power electronics | Serial communication,Electrical efficiency,Ring oscillator,Digital electronics,Computer science,Injection locking,CMOS,Electronic engineering,Multiplexing,Low-power electronics | Conference |
Citations | PageRank | References |
0 | 0.34 | 9 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Kangmin Hu | 1 | 68 | 7.51 |
| Tao Jiang | 2 | 0 | 0.34 |
| Samuel Palermo | 3 | 46 | 7.88 |
| Patrick Yin Chiang | 4 | 150 | 19.20 |