Patrick Yin Chiang

Author Info

Name	Affiliation	Papers
PATRICK YIN CHIANG	Oregon State Univ, Sch EECS, Corvallis, OR 97331 USA	32
Collaborators	Citations	PageRank
129	150	19.20
Referers	Referees	References
533	586	163

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100586

Publications (32 rows)

Collaborators (100 rows)

Referers (100 rows)

Referees (100 rows)

Title	Citations	PageRank	Year
A 56-Gb/s Reconfigurable Silicon-Photonics Transmitter Using High-Swing Distributed Driver and 2-Tap In-Segment Feed-Forward Equalizer in 65-nm CMOS	1	0.36	2022
Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20W/Ch Transmitter, and a 128x128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling	0	0.34	2022
An 8-A Sub-1ns Pulsed VCSEL Driver IC With Built-In Pulse Monitor and Automatic Peak Current Control for Direct Time-of-Flight Applications	0	0.34	2022
Low-Noise Broadband CMOS TIA Based on Multi-Stage Stagger-Tuned Amplifier for High-Speed High-Sensitivity Optical Communication	2	0.38	2019
21.6 A 1.2cm2 2.4GHz self-oscillating rectifier-antenna achieving -34.5dBm sensitivity for wirelessly powered sensors.	3	0.46	2016
Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC.	0	0.34	2016
22.4 A 24Gb/s 0.71pJ/b Si-photonic source-synchronous receiver with adaptive equalization and microring wavelength stabilization	7	0.72	2015
Rate-adaptive compressed-sensing and sparsity variance of biomedical signals	4	0.45	2015
Energy efficiency comparisons of NRZ and PAM4 modulation for ring-resonator-based silicon photonic links	2	0.44	2015
22.6 A 25Gb/s 4.4V-swing AC-coupled Si-photonic microring transmitter with 2-tap asymmetric FFE and dynamic thermal tuning in 65nm CMOS	2	0.50	2015
26.5 An 8-to-16Gb/s 0.65-to-1.05pJ/b 2-tap impedance-modulated voltage-mode transmitter with fast power-state transitioning in 65nm CMOS	2	0.48	2014
A 11μW 250 Hz BW two-step incremental ADC with 100 dB DR and 91 dB SNDR for integrated sensor interfaces	1	0.37	2014
A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS	2	0.41	2014
An 8–16 Gb/s, 0.65–1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning	5	0.53	2014
A 0.47-0.66 pJ/bit, 4.8-8 Gb/s I/O Transceiver in 65 nm CMOS.	1	0.38	2013
A near-threshold, 0.16 nJ/b OOK-transmitter with 0.18 nJ/b noise-cancelling super-regenerative receiver for the medical implant communications service.	11	0.79	2013
Sub-2-ps, Static Phase Error Calibration Technique Incorporating Measurement Uncertainty Cancellation for Multi-Gigahertz Time-Interleaved T/H Circuits.	6	0.62	2012
A near-threshold, multi-node, wireless body area sensor network powered by RF energy harvesting	8	0.71	2012
Innovative approach to server performance and power monitoring in data centers using wireless sensors (invited paper).	1	0.37	2012
A low-power, capacitively-divided, ring oscillator with digitally adjustable voltage swing	0	0.34	2012
A Single-Channel, 1.25-GS/s, 6-bit, 6.08-mW Asynchronous Successive-Approximation ADC With Improved Feedback Delay in 40-nm CMOS	28	2.24	2012
A Comparative Study of 20-Gb/s NRZ and Duobinary Signaling Using Statistical Analysis	1	0.41	2012
0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking.	6	0.68	2012
All-digital 3-50 GHz ultra-wideband pulse generator for short-range wireless interconnect in 40nm CMOS	0	0.34	2011
Low-Power 8gb/S Near-Threshold Serial Link Receivers Using Super-Harmonic Injection Locking In 65nm Cmos	0	0.34	2011
A 90 nm-CMOS, 500 Mbps, 3-5 GHz Fully-Integrated IR-UWB Transceiver With Multipath Equalization Using Pulse Injection-Locking for Receiver Phase Synchronization.	0	0.34	2011
100-phase, dual-loop delay-locked loop for impulse radio ultra-wideband coherent receiver synchronisation.	3	0.50	2011
A 0.6 mW/Gb/s, 6.4–7.2 Gb/s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS	26	1.87	2010
A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories	0	0.34	2010
Short-Range, Wireless Interconnect within a Computing Chassis: Design Challenges	15	1.38	2010
Single-channel, 1.25-GS/s, 6-bit, loop-unrolled asynchronous SAR-ADC in 40nm-CMOS	12	1.10	2010
Sense amplifier power and delay characterization for operation under low-Vdd and low-voltage clock swing	1	0.36	2009