Name
Abstract | ||
|---|---|---|
This work focuses on reducing power consumption while maintaining the efficiency and accuracy of matrix computations using both gorithmic and architectural means. We transform the algorithms, in adaptation to application specifics, to translate the matrix structures into power saving potential via geometric tiling. Instead of using blind tiling, we index and partition matrix elements according to the underlying geometry to claim a better estimate and control of numerical range within and across geometric tiles, which can then be exploited for power saving. |
Year | DOI | Venue |
|---|---|---|
2006 | 10.1109/SOCC.2006.283861 | IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS |
Keywords | Field | DocType |
low power electronics,geometry,matrix computation,numerical range | Power saving,Matrix (mathematics),Computer science,Electronic engineering,Numerical range,Partition (number theory),Matrix multiplication,Computation,Power consumption,Low-power electronics | Conference |
ISSN | Citations | PageRank |
2164-1676 | 7 | 0.61 |
References | Authors | |
1 | 10 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| G. Chen | 1 | 183 | 12.90 |
| Liping Xue | 2 | 25 | 2.43 |
| Jae-Hoon Kim | 3 | 268 | 65.73 |
| Kanwaldeep Sobti | 4 | 51 | 4.23 |
| Lanping Deng | 5 | 68 | 5.91 |
| Xiaobai Sun | 6 | 351 | 39.49 |
| Nikos Pitsianis | 7 | 39 | 6.03 |
| Chaitali Chakrabarti | 8 | 1978 | 184.17 |
| Mahmut T. Kandemir | 9 | 7371 | 568.54 |
| Narayanan Vijaykrishnan | 10 | 6955 | 524.60 |