Paper Info
Title
An Optimized S-Box Circuit Architecture for Low Power AES Design
Abstract
Reducing the power consumption of AES circuits is a critical problem when the circuits are used in low power embedded systems. We found the S-Boxes consume much of the total AES circuit power and the power for an S-Box is mostly determined by the number of dynamic hazards. In this paper, we propose a low-power S-Box circuit architecture: a multi-stage PPRM architecture over composite fields. In this S-Box, (i) the signal arrival times of gates are as close as possible if the depths of the gates from the primary inputs are the same, and (ii) the hazard-transparent XOR gates are located after the other gates that may block the hazards. A low power consumption of 29 碌W at 10 MHz using 0.13 碌m 1.5V CMOS technology was achieved, while the consumptions of the BDD, SOP, and composite field S-Boxes are 275, 95, and 136 碌W, respectively.
Year
DOI
Venue
2002
10.1007/3-540-36400-5_14
CHES
Keywords
Field
DocType
low-power s-box circuit architecture,low power,total aes circuit power,composite field s-boxes,multi-stage pprm architecture,low power consumption,power consumption,optimized s-box circuit architecture,low power aes design,cmos technology,composite field,aes circuit,embedded system
S-box,Electrical load,Advanced Encryption Standard,Computer science,Parallel computing,XOR gate,CMOS,Composite field,Electronic circuit,Electrical engineering,Constant power circuit,Embedded system
Conference
Volume
ISSN
ISBN
2523
0302-9743
3-540-00409-2
Citations 
PageRank 
References 
104
7.51
12
Authors
2
Search Limit
100104
Name
Order
Citations
PageRank
Sumio Morioka149345.23
Akashi Satoh286669.99